1. Field of the Invention
This invention relates to liquid crystal display systems and particularly to liquid crystal display systems including an array of pixel electrodes formed on a semiconductor backplate which are individually addressable through control of field effect switching devices such as metal oxide semiconductor (MOS) transistors.
2. Description of the Related Art
Liquid crystal display systems are known wherein a plurality of individually addressable cells or "pixels" are arranged in a matrix array, with each of the elemental cells of the array operating as a reflective light valve. In the absence of applied potential, the liquid crystal material is clear, and the cell appears dark to an observer. When electric potential above a threshold level is applied across the liquid crystal material, the liquid crystal scatters the light, much like a piece of frosted glass, and the cell appears white to the observer. The percentage of incident light which is scattered towards the viewing area is proportional to the magnitude of the potential applied to the liquid crystal cell, and consequently gray level display presentations may be produced.
In high resolution display systems, a composite presentation is built up from thousands of individually controllable elemental liquid crystal cells, each of which must be updated (the potential across the cell reprogrammed) at a rate sufficiently high to prevent observable flicker in the presentation. This may be accomplished by sandwiching a thin layer of liquid crystal material between a glass plate having a transparent electrode, and a backplate having a matrix array of reflective pixel electrodes formed on a semiconductor wafer. The backplate also contains the individual addressing circuitry and electrical storage circuitry disposed contiguous to the reflective pixel electrode for each cell. Typically, the addressing circuitry has included transistors such as field effect transistors and the storage circuitry has comprised capacitors with the reflective pixel electrode forming one element or plate of the capacitor. Each field effect transistor is utilized to address an associated element of the matrix array, and the associated storage capacitor maintains the applied potential across the liquid crystal cell until the information is updated. An example of this type of construction is disclosed and claimed in U.S. Pat. No. 3,862,360 issued to Dill et al., and assigned to the assignee of the present invention.
As taught in the above-identified Dill et al. patent, one element, or plate, of each storage capacitor may be formed in the semiconductor backplate by ion implantation. As further taught by Dill et al., the reflective pixel electrodes form the top plates of the storage capacitors and a plurality of highly doped areas in the substrate, each disposed under a respective one of the reflective electrodes, serves as the bottom plate of each capacitor.
Liquid crystal display systems of the type just described are reflective displays and therefore require incident light for their operation. The field effect transistors (FET's) used to control the storage capacitors in the backplate are extremely sensitive even to a very low level of incident light. As a result, the ability of the storage capacitors to maintain the applied potential across the liquid crystal cells between pulses is seriously affected by incident light. The shielding effect of the reflective electrodes which lie in a plane between the front of the display and the field effect transistors is insufficient to prevent incident light from discharging the potential on the storage capacitors. This is so because there must be a gap between respective columns and rows of electrodes.
An improved prior art display designed to alleviate adverse effects of incident light is disclosed in U.S. Pat. No. 4,103,297 issued to McGreivy et al. and assigned to the assignee of the present invention. The display of the '297 patent includes a semiconductor backplate having a major surface in which a heavily doped layer is created. An array of openings arranged in a plurality of columns and rows is left in the doped layer and a switching device (FET) is formed in the semiconductor backplate within each opening. A coplanar array of closely spaced reflective back electrodes is disposed above the backplate surface, with each back electrode extending entirely over a respective one of the openings. Means are provided for electrically connecting each of the FET's to the back electrode extending over it. In the preferred embodiment disclosed in the '297 patent, the connecting means comprises an intermediate electrode which is connected to the FET and particularly to its source. The intermediate electrode extends parallel to the semiconductor backplate surface to form a capacitor with the doped layer.
Spaced from the coplanar array of the back electrodes disclosed in the '297 patent is a transparent front electrode supported on a glass plate. Liquid crystal material is confined by appropriate sealing means between the front and back electrodes. Finally, switching devices are provided for applying an actuating voltage between selected ones of the back electrodes and the front electrode in order to effect a pictorial display. These switching devices may be metal oxide semiconductor field effect transistors (MOSFET's) having a source and a drain formed as doped regions in the substrate. Such liquid crystal displays employing MOS switching transistors are referred to as LCMOS displays.
In the prior art, a plurality of equidistant parallel gate buses has been used to activate the switching transistors associated with each display cell, while a plurality of equidistant parallel supply buses has been used to supply the display activating voltage to the switching transistors. Each of the equidistant parallel gate buses is connected to all of the gates of a respective row of switching transistors, while each of the equidistant parallel supply buses is connected to all of the drains of a respective column of switching transistors.
In fabrication of LCMOS displays according to the prior art, the addressing matrix including the MOS switching devices is made with standard P-Channel MOS technology. Building such circuitry using standard silicon processing techniques requires 9 mask steps for establishing source-drain diffusions, channel stop, gate oxide, polysilicon-to-diffusion contacts, polysilicon, light block, metal-to-polysilicon contacts, top metal, and bonding pads. Devices fabricated according to the foregoing processing techniques and structure are subject to line defects caused by one of three mechanisms: photolithography errors (scratches, photo-resist pinholes, bridging particles, etc.), oxide defects which result in polysilicon-to-substrate or diffusion shorts, or excessive leakage from the diffusions to substrate. One of the factors contributing to excessive leakage and shorts in prior art devices is that the supply buses connecting the drains are isolated from the substrate by only a diode breakdown voltage. Such line defects are a source of considerable reduction in production yields and increased production costs.
It has thus appeared desirable to reduce line defects in prior art LCMOS devices. It would be additionally desirable to reduce processing steps and complexity, which contribute to such defects.